Job Description and Requirements
This position targets a Design Engineer for the design, layout, verification and validation of high performance, high speed SERDES circuits.
The successful candidate will work on a variety of tasks, incorporating such tasks as, and not limited to, test bench and specification generation, analog design and layout, documentation, design debug and possibly silicon evaluation.
As a designer of IP layout, circuits will be constructed to facilitate porting to multiple process nodes. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-
house tools supported by an experienced software / CAD team.
Minimum Requirements :
Requires a degree in Engineering or Applied Science (or equivalent) and >
3 years working experience in analog circuit design.
Possesses relevant experience in deep submicron CMOS technologies.
Background in analog and mixed-signal block design, preferably related to high speed SERDES (Drivers, Receivers, Clocking, PLL, DLL, CDR).
Exercises good judgment in selecting efficient / robust methods and techniques to design and validate electronic circuits.
Design for porting (i.e. design to enable ease moving layout across multiple foundry nodes)
Knowledge of signal integrity issues and techniques to mitigate ESD, latchup (i.e. clock / data routes, differential routing, shielding, well distance, substrate biasing)
Familiarity with custom digital layout (i.e. high speed logic paths)
Knowledge of layout effects and design for reliability (i.e. matching, reliability, proximity effects, EM, IR, etc.)
Good written and verbal communication skills and problem solving skills.
Builds productive internal / external working relationships. Networks with senior internal and external personnel in own area of expertise.
Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.
Has familiarity with UNIX operating systems and IC design tools.
Organizational skills are essential.