ASIC Digital Design Engr
Synopsys, Inc
PORTUGAL - Portugal
há 27 dias

Job Description and Requirements

Job Purpose and Mandate :

This position of Digital Design & Verification Engineer is a R&D Engineer whose mandate is to participate in the RTL design and / or verification of digital and / or mixed-

signal logic blocks in compliance with the project’s specifications and Synopsys’ design methodologies.

The successful candidate will work on products that are part of the Synopsys IP portfolio (Serdes Applications) - USB / PCIe / DPHY / MPHY / DP / HDMI, it presents the opportunity for the successful candidate to have their work used in many of the leading products that are developed by Synopsys customers.

Main duties might include :

  • Participate in complex block and / or chip planning and architecture studies
  • Participate in the implementation of mixed-signal blocks using Verilog
  • Participate in the development of verification environments using top of the edge methodologies : System Verilog, VMM and UVM
  • Perform RTL and gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied
  • Perform mixed signal simulations (Analog + Digital)
  • Work towards improving efficiency in design procedures and methodologies
  • Documentation of design and verification environments / plans and overall procedures
  • Other related duties as assigned by the upper manager
  • Development opportunities :

  • Communicate (e-mail, voice, meeting) with customers regarding technical issues
  • Take an active role in moving logic from analog world to digital world
  • Take an active role in implementing new digital blocks or creating verification testcases
  • Take an active role in the definition of new flows

  • Read technical papers and related material to keep abreast of industry progress
  • Write patents for any inventions
  • Minimum Requirements :

  • Requires a degree in Engineering or Applied Science (or equivalent).
  • Knowledge of IC design flows
  • Experience in Verilog / VHDL. Knowledge of SystemVerilog or VMM or OVM or UVM would be advantageous
  • Experience in producing high-quality technical documentation
  • A successful track record in project work
  • Communicate effectively with other team members
  • Organizational skills
  • Willingness to learn new things
  • Increva-se
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