Senior ASIC Digital Verification Engineer
Synopsys
Porto, PORTUGAL
há 4 dias

and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.

The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.

All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.

And get differentiated products to market quickly with reduced risk.

ASIC Digital Verification Engineer

Does this sound like a good role for you?

Seeking a highly motivated and innovative digital design / verification engineer with theoretical background in memory controllers.

The successful candidate will work on product development for High Bandwidth Memory (HBM) Controllers or similar protocols.

Working as part of an experienced digital design and verification team, the candidate will be involved in designing and verifying current and next generation products.

The position offers an excellent opportunity to work with experts on these fields on designs from specification development to performing functional, performance and interop tests.

The candidate will be working on :

  • Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc )
  • Generate verification test plan, verification environment documentation and test environment usage documentation
  • Define, develop, and verify complex UVM verification environments
  • Evaluates and exercises various aspects of the development flow which may include such items as Verilog / SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage)
  • Identify design problems, possible corrective actions and / or inconsistencies on documented functionality
  • Key Qualifications

  • Strong desire to learn and explore new state of the art technologies
  • Demonstrate good written and spoken English communication skills
  • Demonstrate good analysis and problem-solving skills
  • Experience with Verilog, VHDL and / or SystemVerilog
  • Experience with scripting languages (BASH / TCSH / PERL / PYTHON / TCL) is a plus
  • Exposure to synthesis and static timing, Lint, CDC, Formal checking flow is a plus
  • Understanding of verification methodology such as UVM is a plus
  • Good organization and communication skills
  • 6+ years of relevant experience
  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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