Lisbon in Portugal offers a new challenging opportunity for a seasoned Analog IC Layout Engineer to prove themselves in supporting the Layout team of a leading provider of ASIC's and embedded systems for connected IoT networks for industrial, consumer, communications and medical applications.
You will be working in a team of Layout Engnieers on the layout of Analog Mixed Signal blocks like ADCs, DACs, PLLs, Buffers, Bandgaps, LDOs, Oscillators and IP blocks and will be responsible for floorplanning, block-
level layout, noise isolation, parasitic extraction, toplevel integration and physical verification of designs on leading edge technologies down to 28nm.
As the successful applicant you will be industry degree qualified in Electronic Engineering plus a couple of years of experience in Analog Mixed Signal IC Layout in a Cadence environment at both block and IC top level.
Experience in the layout of Analog Mixed Signal IC's such as ADCs, DACs, PLLs, Buffers, Bandgaps, LDOs, Oscillators is beneficial to your application and you should know about IO ring placement and IC-level floorplanning.
You should also have a good understanding of ESD, Latch-Up and antenna layout techniques as well as experience with Electromigration, IR-
Drop, RC delay and DFM layout.
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